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IBM killing Silicon - Inside IBM's Carbon nanotube computer chip lab

Recent research from IBM's Watson Research Centre in Yorktown Heights, New York, where some of the world's best physicists, chemists and nano-engineers reside are endeavouring to create the first high-density and self-assembling Carbon nanotube (CNT) computer chip process.  In many ways similar to how Jack Kilby at Texas Instruments discovered the monolithic VLSI process for fabricating Silicon (Si) chips in 1958, which in a way explains IBM's urgency to find a process that enables the first known creation of a CNT computer chip.

DCN Corp® - Metal pads, covering small Carbon nanotubes (CNT) (in the middle).  Credit - IBM

In the next decade or so - the goalposts for semiconductor fabrication will shift, whereby Si will be expected to reach a miniaturization "road-block".  To that point - it is claimed by many respected commentators that we simply will not be able to make Si transistors any smaller, and so when the Si road-block does happen there will be a few materials seeking to fill the void - most notably Si-Germanium, Galium Arsenide, and various forms of Carbon (C), such as nanotubes, nanowires, Graphene.  In practical terms - future computer chips fabricated from CNTs will be massively desirable - potentially they would be many times faster than Si, consume less power, and can be scaled down to just a couple of nanometers (nm).  In reality working with CNTs - as like Graphene - is seeming rather difficult - primarily because of the lack of knowledge.

Moving forward - progress is still being made, as is the case with IBM, whereby they have managed to create a 10,000 CNT transistor chip - directly on top of a standard Si wafer base substrate.  Such a R&D stride is significant for two reasons:-

  • The process employed is very similar to existing Si chip fabrication processes, which in terms of implementation and subsequent industrialisation is very good
  • IBM is reporting that its density of individually positioning CNTs is two orders of the magnitude higher than any other research group's efforts

Nonetheless, there still remains a lot of work to be done.  For instance the CNT transistors are currently spaced 150 nm apart, which is much further than in traditional Si chips and will need to be reduced to reach the required feature density.  The other problem is that the entire chip of 10,000 transistors currently only has one gate - the Si wafer base substrate itself.  Every transistor turns on and off at the same time.  To amend this, the IBM researchers need to add electrodes to each of the CNTs - a step that also hinders the mass manufacturing of Graphene-based transistors.  This is one of the key steps that IBM and other Si Valley conglomerates are working on.  Original article available here.

Below are a few more pictures of IBM's CNT computer chip fabrication process:-


DCN Corp® - CNTs are produced by burning carbon with an electric arc - about one quarter of the soot is nanotubes.  Credit - IBM


DCN Corp® - After the wafer is etched with trenches, it receives two liquid baths to deposit the CNTs.  Credit - IBM


DCN Corp® - An IBMer, sliding the CNT transistor wafer into a testing machine.  Credit - IBM


DCN Corp® - Black electrical probes, testing the CNT transistors (not visible).  Credit - IBM

IBM's CNT research breakthrough is extremely positive - especially when considering that DCN Corp could achieve the same results by homogeneously dip coating as well as providing the desired nano-density (< 150nm).  Therefore, if you or your colleagues are interested in making the above a reality - please ensure to contact the company as soon as practicably possible.